OpenCSD - CoreSight Trace Decode Library  1.3.3
trc_mem_acc_cache.h
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1 
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34 
35 #ifndef ARM_TRC_MEM_ACC_CACHE_H_INCLUDED
36 #define ARM_TRC_MEM_ACC_CACHE_H_INCLUDED
37 
38 #include <string>
39 #include "opencsd/ocsd_if_types.h"
40 
41 #define MEM_ACC_CACHE_PAGE_SIZE 256
42 #define MEM_ACC_CACHE_MRU_SIZE 12
43 
44 class TrcMemAccessorBase;
45 class ITraceErrorLog;
46 
47 typedef struct cache_block {
49  uint32_t valid_len;
52 
53 // enable define to collect stats for debugging / cache performance tests
54 //#define LOG_CACHE_STATS
55 
56 
59 {
60 public:
63 
64  void enableCaching(bool bEnable) { m_bCacheEnabled = bEnable; };
65  void invalidateAll();
66  const bool enabled() const { return m_bCacheEnabled; };
67  const bool enabled_for_size(const uint32_t reqSize) const
68  {
69  return (m_bCacheEnabled && (reqSize <= MEM_ACC_CACHE_PAGE_SIZE));
70  }
71 
72 
74  ocsd_err_t readBytesFromCache(TrcMemAccessorBase *p_accessor, const ocsd_vaddr_t address, const ocsd_mem_space_acc_t mem_space, const uint8_t trcID, uint32_t *numBytes, uint8_t *byteBuffer);
75 
78 
79 private:
80  bool blockInCache(const ocsd_vaddr_t address, const uint32_t reqBytes); // run through each page to look for data.
81  bool blockInPage(const ocsd_vaddr_t address, const uint32_t reqBytes);
82  void logMsg(const std::string &szMsg);
83 
85  int m_mru_idx = 0; // in use index
86  int m_mru_next_new = 0; // next new page at this index.
87  bool m_bCacheEnabled = false;
88 
89 #ifdef LOG_CACHE_STATS
90  uint32_t m_hits = 0;
91  uint32_t m_misses = 0;
92  uint32_t m_pages = 0;
93  uint32_t m_hit_rl[MEM_ACC_CACHE_MRU_SIZE];
94  uint32_t m_hit_rl_max[MEM_ACC_CACHE_MRU_SIZE];
95 #endif
96 
97  ITraceErrorLog *m_err_log = 0;
98 };
99 
101 {
102  for (int i = 0; i < MEM_ACC_CACHE_MRU_SIZE; i++)
103  {
104  m_mru[i].st_addr = 0;
105  m_mru[i].valid_len = 0;
106 #ifdef LOG_CACHE_STATS
107  m_hit_rl[i] = 0;
108  m_hit_rl_max[i] = 0;
109 #endif
110  }
111 }
112 
113 inline bool TrcMemAccCache::blockInPage(const ocsd_vaddr_t address, const uint32_t reqBytes)
114 {
115  if ((m_mru[m_mru_idx].st_addr <= address) &&
116  m_mru[m_mru_idx].st_addr + m_mru[m_mru_idx].valid_len >= (address + reqBytes))
117  return true;
118  return false;
119 }
120 
121 inline bool TrcMemAccCache::blockInCache(const ocsd_vaddr_t address, const uint32_t reqBytes)
122 {
123  int tests = MEM_ACC_CACHE_MRU_SIZE;
124  while (tests)
125  {
126  if (blockInPage(address, reqBytes))
127  return true; // found address in page
128  tests--;
129  m_mru_idx++;
130  if (m_mru_idx == MEM_ACC_CACHE_MRU_SIZE)
131  m_mru_idx = 0;
132  }
133  return false;
134 }
135 
137 {
138  for (int i = 0; i < MEM_ACC_CACHE_MRU_SIZE; i++)
139  {
140  m_mru[i].valid_len = 0;
141  m_mru[i].st_addr = 0;
142  }
143  m_mru_idx = 0;
144  m_mru_next_new = 0;
145 }
146 
147 #endif // ARM_TRC_MEM_ACC_CACHE_H_INCLUDED
148 
149 /* End of File trc_mem_acc_cache.h */
Error logging interface.
const bool enabled_for_size(const uint32_t reqSize) const
ocsd_err_t readBytesFromCache(TrcMemAccessorBase *p_accessor, const ocsd_vaddr_t address, const ocsd_mem_space_acc_t mem_space, const uint8_t trcID, uint32_t *numBytes, uint8_t *byteBuffer)
const bool enabled() const
void logAndClearCounts()
void setErrorLog(ITraceErrorLog *log)
void enableCaching(bool bEnable)
Memory range to access by trace decoder.
enum _ocsd_mem_space_acc_t ocsd_mem_space_acc_t
enum _ocsd_err_t ocsd_err_t
uint64_t ocsd_vaddr_t
OpenCSD : Standard Types used in the library interfaces.
uint8_t data[MEM_ACC_CACHE_PAGE_SIZE]
uint32_t valid_len
ocsd_vaddr_t st_addr
#define MEM_ACC_CACHE_PAGE_SIZE
struct cache_block cache_block_t
#define MEM_ACC_CACHE_MRU_SIZE