OpenCSD - CoreSight Trace Decode Library  1.3.3
trc_cmp_cfg_ptm.h
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1 /*
2  * \file trc_cmp_cfg_ptm.h
3  * \brief OpenCSD :
4  *
5  * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
6  */
7 
8 
9 /*
10  * Redistribution and use in source and binary forms, with or without modification,
11  * are permitted provided that the following conditions are met:
12  *
13  * 1. Redistributions of source code must retain the above copyright notice,
14  * this list of conditions and the following disclaimer.
15  *
16  * 2. Redistributions in binary form must reproduce the above copyright notice,
17  * this list of conditions and the following disclaimer in the documentation
18  * and/or other materials provided with the distribution.
19  *
20  * 3. Neither the name of the copyright holder nor the names of its contributors
21  * may be used to endorse or promote products derived from this software without
22  * specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27  * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
28  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  */
35 
36 #ifndef ARM_TRC_CMP_CFG_PTM_H_INCLUDED
37 #define ARM_TRC_CMP_CFG_PTM_H_INCLUDED
38 
39 #include "trc_pkt_types_ptm.h"
40 #include "common/trc_cs_config.h"
41 
62 class PtmConfig : public CSConfig // public ocsd_ptm_cfg
63 {
64 public:
66  PtmConfig(const ocsd_ptm_cfg *cfg_regs);
67  ~PtmConfig() {};
69  /* register bit constants. */
70  static const uint32_t CTRL_BRANCH_BCAST = (0x1 << 8);
71  static const uint32_t CTRL_CYCLEACC = (0x1 << 12);
72  static const uint32_t CTRL_TS_ENA = (0x1 << 28);
73  static const uint32_t CTRL_RETSTACK_ENA = (0x1 << 29);
74  static const uint32_t CTRL_VMID_ENA = (0x1 << 30);
75 
76  static const uint32_t CCER_TS_IMPL = (0x1 << 22);
77  static const uint32_t CCER_RESTACK_IMPL = (0x1 << 23);
78  static const uint32_t CCER_DMSB_WPT = (0x1 << 24);
79  static const uint32_t CCER_TS_DMSB = (0x1 << 25);
80  static const uint32_t CCER_VIRTEXT = (0x1 << 26);
81  static const uint32_t CCER_TS_ENC_NAT = (0x1 << 28);
82  static const uint32_t CCER_TS_64BIT = (0x1 << 29);
83 
84 // operations to convert to and from C-API structure
85 
87  PtmConfig & operator=(const ocsd_ptm_cfg *p_cfg);
88 
90  operator const ocsd_ptm_cfg &() const { return m_cfg; };
92  operator const ocsd_ptm_cfg *() const { return &m_cfg; };
93 
94 // access functions
95 
96  const bool enaBranchBCast() const;
97  const bool enaCycleAcc() const;
98 
99  const bool enaRetStack() const;
100  const bool hasRetStack() const;
101 
102  const int MinorRev() const;
103 
104  const bool hasTS() const;
105  const bool enaTS() const;
106  const bool TSPkt64() const;
107  const bool TSBinEnc() const;
108 
109  const int CtxtIDBytes() const;
110  const bool hasVirtExt() const;
111  const bool enaVMID() const;
112 
113  const bool dmsbGenTS() const;
114  const bool dmsbWayPt() const;
115 
116  virtual const uint8_t getTraceID() const;
117 
118  const ocsd_core_profile_t &coreProfile() const { return m_cfg.core_prof; };
119  const ocsd_arch_version_t &archVersion() const { return m_cfg.arch_ver; };
120 
121 private:
122  ocsd_ptm_cfg m_cfg;
123 };
124 
125 /* inlines */
126 
128 {
129  // object of base class ocsd_ptm_cfg
130  m_cfg = *p_cfg;
131  return *this;
132 }
133 
134 inline const bool PtmConfig::enaBranchBCast() const
135 {
136  return (bool)((m_cfg.reg_ctrl & CTRL_BRANCH_BCAST) != 0);
137 }
138 
139 inline const bool PtmConfig::enaCycleAcc() const
140 {
141  return (bool)((m_cfg.reg_ctrl & CTRL_CYCLEACC) != 0);
142 }
143 
144 inline const bool PtmConfig::enaRetStack() const
145 {
146  return (bool)((m_cfg.reg_ctrl & CTRL_RETSTACK_ENA) != 0);
147 }
148 
149 inline const bool PtmConfig::hasRetStack() const
150 {
151  return (bool)((m_cfg.reg_ccer & CCER_RESTACK_IMPL) != 0);
152 }
153 
154 inline const int PtmConfig::MinorRev() const
155 {
156  return ((int)m_cfg.reg_idr & 0xF0) >> 4;
157 }
158 
159 inline const bool PtmConfig::hasTS() const
160 {
161  return (bool)((m_cfg.reg_ccer & CCER_TS_IMPL) != 0);
162 }
163 
164 inline const bool PtmConfig::enaTS() const
165 {
166  return (bool)((m_cfg.reg_ctrl & CTRL_TS_ENA) != 0);
167 }
168 
169 inline const bool PtmConfig::TSPkt64() const
170 {
171  if(MinorRev() == 0) return false;
172  return (bool)((m_cfg.reg_ccer & CCER_TS_64BIT) != 0);
173 }
174 
175 inline const bool PtmConfig::TSBinEnc() const
176 {
177  if(MinorRev() == 0) return false;
178  return (bool)((m_cfg.reg_ccer & CCER_TS_ENC_NAT) != 0);
179 }
180 
181 inline const bool PtmConfig::hasVirtExt() const
182 {
183  return (bool)((m_cfg.reg_ccer & CCER_VIRTEXT) != 0);
184 }
185 
186 inline const bool PtmConfig::enaVMID() const
187 {
188  return (bool)((m_cfg.reg_ctrl & CTRL_VMID_ENA) != 0);
189 }
190 
191 inline const bool PtmConfig::dmsbGenTS() const
192 {
193  return (bool)((m_cfg.reg_ccer & CCER_TS_DMSB) != 0);
194 }
195 
196 inline const bool PtmConfig::dmsbWayPt() const
197 {
198  return (bool)((m_cfg.reg_ccer & CCER_DMSB_WPT) != 0);
199 }
200 
201 inline const uint8_t PtmConfig::getTraceID() const
202 {
203  return (uint8_t)(m_cfg.reg_trc_id & 0x7F);
204 }
205 
208 #endif // ARM_TRC_CMP_CFG_PTM_H_INCLUDED
209 
210 /* End of File trc_cmp_cfg_ptm.h */
Base class for configuration data on CoreSight trace component.
Definition: trc_cs_config.h:50
Interpreter class for PTM Hardware configuration.
const ocsd_arch_version_t & archVersion() const
const int CtxtIDBytes() const
number of context ID bytes traced 1,2,4;
static const uint32_t CCER_VIRTEXT
PtmConfig(const ocsd_ptm_cfg *cfg_regs)
static const uint32_t CCER_RESTACK_IMPL
static const uint32_t CTRL_VMID_ENA
static const uint32_t CCER_DMSB_WPT
static const uint32_t CCER_TS_64BIT
static const uint32_t CCER_TS_IMPL
static const uint32_t CTRL_CYCLEACC
static const uint32_t CCER_TS_ENC_NAT
static const uint32_t CCER_TS_DMSB
const ocsd_core_profile_t & coreProfile() const
static const uint32_t CTRL_RETSTACK_ENA
static const uint32_t CTRL_BRANCH_BCAST
static const uint32_t CTRL_TS_ENA
enum _ocsd_core_profile ocsd_core_profile_t
enum _ocsd_arch_version ocsd_arch_version_t
const bool enaRetStack() const
return stack enabled.
const bool TSPkt64() const
timestamp packet is 64 bits in size.
PtmConfig & operator=(const ocsd_ptm_cfg *p_cfg)
copy assignment operator for base structure into class.
const bool enaVMID() const
VMID tracing enabled.
const bool enaBranchBCast() const
Branch broadcast enabled.
const bool dmsbGenTS() const
TS generated for DMB and DSB.
const bool TSBinEnc() const
Timestamp encoded as natural binary number.
const int MinorRev() const
return X revision in 1.X
const bool dmsbWayPt() const
DMB and DSB are waypoint instructions.
const bool enaTS() const
Timestamp trace is enabled.
const bool hasVirtExt() const
processor has virtualisation extensions.
const bool enaCycleAcc() const
cycle accurate tracing enabled.
const bool hasRetStack() const
return stack implemented.
virtual const uint8_t getTraceID() const
CoreSight Trace ID for this device.
const bool hasTS() const
Timestamps implemented in trace.
ocsd_core_profile_t core_prof
ocsd_arch_version_t arch_ver